Exploration of Memory and Cluster Modes in Directory-based Many-core CMPs


Conference
NOCS 2018

Authors
Subodha Charles Chetan Arvind Patil Umit Y. Ogras Prabhat Mishra

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IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Torino, Italy, October 4-5, 2018


Abstract

Networks-on-chip have become the standard interconnect solution to address the communication requirements of many-core chip multiprocessors. It is well-known that network performance and power consumption depend critically on the traffic load. The network traffic itself is a function of not only the application, but also the cache coherence protocol, and memory controller/directory locations. Communication between the distributed directory to memory can introduce hotspots, since the number of memory controllers is much smaller than the number of cores. Therefore, it is critical to account for directorymemory communication, and model them accurately in architecture simulators. This paper analyzes the impact of directorymemory traffic and different memory and cluster modes on the NoC traffic and system performance. We demonstrate that unrealistic models in a widely used multiprocessor simulator produce misleading power and performance predictions. Finally, we evaluate different memory and cluster modes supported by Intel Xeon-Phi processors, and validate our models on four different cache coherence protocols.

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A researcher (University of Moratuwa), entrepreneur (Alta Vision Pvt. Ltd.) and a volunteer (IEEE).

© 2021 Subodha Charles. All rights reserved.